This invention relates to semiconductor memory devices and, more particularly, to a technology effective in utilizing for a Y-system-relief technology on a dynamic RAM (Random Access Memory) of so-called a one-cross-point scheme having dynamic memory cells arranged at cross points between the word lines and the bit lines.
In the research done after completing the present invention, there have been revealed Japanese Patent Laid-open No. 178698/1984 (hereinafter, referred to as Prior Art 1) and Japanese Patent Laid-open No. 20300/1986 (hereinafter, referred to as Prior Art 2) as the dynamic-RAM redundant relief technologies of the open-bit-line type (one-cross-point scheme), hereinafter explained, considered related to the present invention. The publication of Prior Art 1 discloses a 64K-bit dynamic RAM provided with spare arrays. The publication of Prior Art 2 discloses a one-cross-point dynamic type memory provided with a redundant relief circuit. However, there found no conception that a plurality of memory mats are provided in a direction of the bit line to effectively relieve a failed bit line on a mat-by-mat basis as disclosed in the dynamic RAM according to the present invention, hereinafter referred.
Various methods for memory relief are disclosed in the following references, Japanese Patent Laid-Open Nos. 151895/1985, 1511896/1985, 60489/1983, 77946/1986, 151899/1986 and 219597/1999.